Chelsio Adopts Synopsys DesignWare 56G Ethernet PHY IP to Accelerate Development of High-Performance Computing SoC

Synopsys, Inc. today announced that Chelsio has adopted its silicon-proven DesignWare® 56G Ethernet PHY IP to accelerate development of Chelsio's System-on-Chip (SoC) design targeting high-performance smart network interface card (NIC) and server applications. Chelsio selected the Synopsys DesignWare 56G Ethernet PHY IP due to its support for a wide range of data rates from 1.25 Gbps to 56 Gbps across standards such as Ethernet, PCI Express, OIF, and JESD. The DesignWare 56G Ethernet PHY with firmware-controlled algorithms including continuous calibration and adaptation (CCA) delivers robust performance across a range of voltage and temperature variations.