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Cadence Partners with Arm to Speed Up Hyperscale Computing and 5G Communications SoC Development

Cadence Design Systems, Inc. today announced an expansion of its partnership with Arm to accelerate hyperscale computing and 5G communications SoC growth using Cadence tools and the new Arm NeoverseTM V1 and Neoverse N2 platforms. Cadence streamlined its digital and verification full flows to accelerate the adoption of these latest platforms, building on previous silicon successes in which leading customers used the first-generation Arm Neoverse N1 platform and Cadence digital and verification tools on 7nm process technologies. Cadence also provided extensive 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to assist customers in maximizing power, performance, and area (PPA) goals and improve productivity.

Digital Full Flow and RAKs

Cadence's optimized digital full flow has been demonstrated on a 5nm, 4GHz Neoverse V1 implementation, providing cutting-edge performance—an important capability of the Neoverse platforms. Customers operating on advanced-node designs, such as 3D-IC chiplets, will use the latest Cadence 5nm and 7nm RAKs to more efficiently implement data center server-class CPUs and reduce time to tapeout. The GenusTM Synthesis Solution, Modus DFT Software Solution, InnovusTM Implementation System, QuantusTM Extraction Solution, TempusTM Timing Signoff Solution, and ECO Choice, VoltusTM IC Power Integrity Solution, Conformal® Equivalence Checking, and Conformal Low Power comprise the full Cadence RTL-to-GDS RAKs.

The digital full flow provides some key features to speed the delivery of 5nm and 7nm server-class designs, including:

• Cadence iSpatial technology, which provides an integrated, predictable implementation flow for faster design closure

• Integrated Tempus timing and Voltus IR analysis for true power integrity-driven timing signoff and optimization, which enables designers to deliver more reliable devices

• The Tempus ECO Option offers signoff-accurate final design closure using path-based optimization to achieve optimal PPA

Verification Full Flow and Engines

Companies developing Arm Neoverse-based SoCs will achieve the highest SoC-level verification throughput by using Cadence's verification full flow, in addition to gaining from Cadence's validated 5nm, 4GHz digital full flow. The Cadence System VIP solution, in particular, has been improved with checkers, verification plans, and traffic generators to validate Arm Neoverse-based SoC coherency, performance, and Arm SystemReady compliance. All Cadence verification engines, comprising Xcelium™ Logic Simulation, Palladium® Z1 Emulation, Protium™ X1 Prototyping, and JasperGold® Formal Verification, are leveraged by these System VIP extensions to deliver a comprehensive SoC-level verification flow for Arm Neoverse-based SoCs.

Customers benefit from a faster path to design closure and enhanced predictability with the Cadence digital full flow. Cadence's verification full flow is made up of best-in-class engines, verification fabric technologies, and solutions that increase verification throughput. Cadence flows help customers achieve design innovation by supporting the wider Cadence Intelligent System DesignTM approach.

About Cadence

Cadence is a major leader in electronic design, with over 30 years of computational software expertise. The organization uses its fundamental Intelligent System Design strategy to deliver software, hardware, and intellectual property that make design ideas a reality. Cadence clients are the most visionary companies in the world, offering exceptional electronic devices ranging from chips to boards to solutions for the most competitive market applications such as consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, retail, and healthcare. Cadence has been named one of the 100 Best Companies to Work With by Fortune magazine for the last seven years.

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